Key Responsibilities:
- Define, document, develop and execute RTL verification test/coverage for extremely parameterized IPs in Python and C++, capable of running on any available RTL simulator (Cadence, Synopsys, etc.).
- Maintain and improve verification workflow, improve metrics and increase automation.
- Implement verification components such as BFMs or monsters. such as BFMs or monitors used in verification test benches.
Required Experience / Qualifications:
- At least 4 years of industry experience as a verification engineer.
- Understanding of hardware RTL design and verification languages (VHDL, Verilog, SystemC, C++, Python, SystemVerilog).
- Strong experience in the use and development of verification methods and infrastructure (VIPs, UVMs, testbeds, EDA tools).
- Experience in formal proof verification methodology is a plus
- Shell scripting
- Knowledge of interconnect technology is a plus
- Understanding of hardware communication protocols (AMBA, OCP, others)
- Good written and oral communication in French and English.
- Curious, autonomous, rigorous and results-oriented, with a commitment to quality and a thorough approach to work.
- Proven ability to work well in a team environment
Educational Requirements:
- Master’s degree or Doctorate in engineering or computer science
Learn more at arteris.com.
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