Job Details:

Job Description: 

The GPU HW IP Poland team located in Gdańsk is looking for an energetic and passionate HW IP Verification Engineer/Verification Architect to work in front end area of HW IP development for Intel's next generation AI/GPU chips/and SOCs for the different market segments.

In this role, the candidate supports Technical Leadership in the HW IP design and verification and overall definition, modelling, implementation and documentation for IP and SoC sub-system development.

You will also support teams of design engineers, system architects, micro-architects, and verification engineers to ensure that the design is implemented to specification.

Key Responsibilities:

• Developing test strategy, testing plan, performing behavioural and/or performance modelling of new features and configurations, and conducting analysis of results using advanced statistics and data predictions for benchmarking and determining ROI of areas for improvement
• Collaborating with architects, design engineers, verification engineers, and research teams to improve the overall design of GPU and overcome performance bottlenecks and constraints
• Working hand in hand with pre-silicon and post-silicon teams to debug, root cause, and identify workarounds and solutions for critical failures
• Driving GPU functionality, connectivity, configuration, performance, timing, power, and area goals
• Evaluating feasibility trade-offs and exploring and defining new approaches and novel architectures for GPU
• Providing experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints
• Developing and driving end-to-end GPU architecture specifications across graphics, compute, media, or display for highly optimized, modular, and scalable GPU
• Conducting competitive analysis and standards efforts, industry trends, and customer requests to develop a hardware and software feature roadmap meeting platform needs
• Ensuring interoperability of hardware and software throughout the product life cycle
• Delivering optimized GPU for multiple segments spanning from ultralow power through client and into high performance GPU, super compute, and customized GPU offerings
• Reviewing, challenging, and influencing cross-functional roadmaps and defining technology targets for future GPUs

Qualifications:

Minimum Requirements:

• Master’s or PhD degree in Electronics/Electrical Engineering/Computer Science
• 7+ years of ASIC design and verification industry experience
• 5+ years of experience as Architect / Verification Architect / Verification Tech Lead with:
  • Proven track of record in full design and verification cycle from specification to silicon (completed/shipped commercial projects, demos, patents, publications, etc.)
  • Extensive knowledge of Verilog and System Verilog and working knowledge of UVM methodology
  • Good understanding of functional verification
    • Experience in verification strategy and test planning / directed and stress test generation / good knowledge of functional and code coverage/verification infrastructures and verification and/or debug flows
    • Fundamentals of state machine verification
    • Complex protocol verification
  • Knowledge of co-simulation using SV/DPI or other tools
  • Adept in programming and/or scripting (C++, Perl and others) and conversant with flows and tools for VLSI logic design and/or functional verification
  • Expertise in C/C++ modelling (best if using Algorithmic C / AC-types)
  • Experience in multi-power domain / multi-clock domain designs and CDC
  • Functional and power/performance optimization / and verification (experience in considerations for power, performance and cost optimization is desirable)
  • Experience in Formal Verification
    • Expert in SVA (SystemVerilog assertions)
    • Experience in Formal Verification: control and data path /FPV and DPV

• Knowledge of CPU/GPU hardware architectures and components, and GPU hardware pipeline
• Knowledge of 3D graphics theory, rendering algorithms and techniques used in games.
• Experience in reading and writing technical documentation (high-level spec and micro-architecture spec is desirable)
• Ability to work effectively with both internal and external teams and stakeholders, have strong problem-solving and good communication skills (English and Polish)
• Experience in mentoring junior engineers, as well as the ability to drive more complex tasks

Nice to have:

• Experience with Synopsys and Cadence tools
• Knowledge of SoC and Platform level product architectures

What We Offer? 

At Intel, employees share in successes, enjoy comprehensive rewards and are inspired by an innovative & inclusive workplace. What can you expect when there is a match between us?

• We guarantee you will be working in a safe environment - either at your own home or in our premises if needed, the security and wellbeing of you and your family stands as our utmost responsibility.

• You will have constant opportunities to develop your professional career through technical and soft skills training, taking part in innovation projects or rotational programs

• Flexible working hours are important to us

• Our Amazing Benefits to make life easier and more enjoyable are waiting for you: Stock Program, Annual and Quarterly Bonuses, Employee Pension Plan, Medical Plan and life insurance for you and your Family, Peer to peer recognition, Ticket restaurant Card, Multisport Card / Holiday card, Groups of enthusiasts, Exclusive employee discounts, (online) events and many more.

• Rewards Experience @ Intel Poland: https://jobs.intel.com/pl/benefits

* Job posting details (such as work model, location or time type) are subject to change.

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Position of Trust

Work Model for this Role